Metal interconnects connect gates and other devices in electronic circuitry, and are having an increasing large role in ASICS (Application Specific Integrated Circuit) in terms of performance and manufacturing. In deep sub-micron ASIC design, for instance, interconnects are overtaking the transistor as being the dominant factor affecting performance. That is, full performance of an ASIC design cannot be realized if the metal interconnects comprising the circuits are not optimized.
Global chip interconnects, for example, are critically important signal lines comprising a circuit. Global interconnects form the critical connections of the circuit and may have long lengths (usually more than 3 mm). Example uses of global interconnects include long inter-block wires, busses, and clock nets.
There are three main signal integrity problems to be addressed for global interconnects. The first problem is signal delay minimization; the second problem is signal ramptime (slop) minimization; and the third problem is parasitic (coupling) impact from other wires. Designers have attempted to address each of these problems using varying approaches.
FIG. 1 is a diagram illustrating a conventional approach for addressing signal delay minimization. Typically, one or more buffers 12 (or inverters) are inserted into the global interconnect 10. Another approach has been to increase the wire width, or a combination of both. Buffer insertion speeds up the interconnect, but only untill some particular number of buffers is inserted. Buffers 12 also reduce ramptimes, and the global interconnect 10 becomes less sensitive to influence of other wires.
FIG. 2 is a diagram illustrating a conventional approach for addressing parasitic problem. In this approach, guard wires 14 are placed on one or both sides of the global interconnect 10 and other signal traces to protect against influence of other wires, or to increase the spacing between wires, or both. The guard wires 14 are connected to either power or ground, and are therefore referred to as passivie shielding (i.e., no signal is transmitted across the wires).
Both approaches described above can be combined. For example, FIG. 3 is a diagram showing additional buffers 12 inserted on a global interconnect 10, plus the use of passive shielding guard wires 14.
The main drawback of the use of buffers 12 is that buffers have internal delays and, thus, the signal delay across the global interconnect 10 cannot be decreased more than about two times. Another limitation of buffers 12 is that often a device includes macro blocks, which are pre-designed blocks of circuits. In some designs, a top (chip) level global interconnect 10 or other wire is routed over a hard macro block in a metal layer on top of the metal layers used for the hard macro block. However, buffers cannot be inserted in this wire because buffers cannot be placed (implemented) within hard macro blocks.
There are other approaches for addressing signal integrity issues. For example, some have attempted to address the signal delay problem using boosters. In this approach, a special additional circuit (booster) used to enhance the signal across the global interconnect 10. The booster, however, is complex and must be connected to the original interconnect 10. In addition, this approach does not address the problem of parasitic impact.
One approach for addressing the parasitic problem is the use of differential signals. This is a complex approach requiring two lines of signals, complex drivers and receiver cells, special connectors, and usually guard wires as well. For example, U.S. Pat. No. 6,293,827 describes special connectors for differential signals. Although useful, this approach does not solve the problem of parasite impact.
Accordingly, what is needed is an improved distribution system for global interconnect that increases the signal integrity. The present invention addresses such a need.